The Instruction Register Is Used To Store Which Of The Following?

Instruction Register

Access of the instruction register to the status register allows for conditional branching or conditional subroutines.

From: Solar Energy Conversion , 1979

Simple Embedded Processors

Peter Wilson , in Design Recipes for FPGAs (Second Edition), 2016

8.3.3 The Instruction Register

The instruction register (IR) has the same clock and reset signals as the PC, and also the same interface to the bus (IR_bus) defined as a std_logic_vector of type INOUT. The IR also has two further control signals, the first being the command to load the instruction register (IR_load), and the second being to load the required address onto the system bus (IR_address). The final connection is the decoded opcode that is to be sent to the system controller. This is defined as a simple unsigned integer value with the same size as the basic system bus. The basic VHDL for the entity of the IR is given as follows:

1 library ieee;

2 use ieee . std_logic_1164 . all;

3 use work . processor_functions . all;

4 entity ir is

5 port (

6 clk : in std_logic;

7 nrst : in std_logic;

8 ir_load : in std_logic;

9 ir_valid : in std_logic;

10 ir_address : in std_logic;

11 ir_opcode : out opcode;

12 ir_bus : inout std_logic_vector (n −1 downto 0)

13 );

14 end entity ir;

The function of the IR is to decode the opcode in binary form and then pass to the control block. If the IR_valid is low, the the bus value should be set to Z for all bits. If the reset signal (nsrt) is low, then the register value internally should be set to all 0s.

On the rising edge of the clock, the value on the bus shall be sent to the internal register and the output opcode shall be decoded asynchronously when the value in the IR changes. The resulting VHDL architecture is given here:

1 architecture rtl of ir is

3 signal ir_internal : std_logic_vector (n −1 downto 0);

4 begin

5 ir_bus <= ir_internal

6 when ir_valid = 1 else (others => z);

7 ir_opcode <= decode (ir_internal);

8 process (clk, nrst) is

9 begin

10 if nrst = 0 then

11 ir_internal <= (others => 0);

12 elsif rising_edge (clk) then

13 if ir_load = 1 then

14 ir_internal <= ir_bus;

15 end if;

16 end if;

17 end process;

18 end architecture rtl;

In this VHDL, notice that we have used the predefined function Decode from the processor_functions package previously defined. This will look at the top 4 bits of the address given to the IR and decode the relevant opcode for passing to the controller.

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PIC Architecture

Martin Bates , in PIC Microcontrollers (Third Edition), 2011

5.2.2 Instruction Execution

The program execution section of the MCU contains the instruction register, instruction decoder, and timing and control logic. The 14-bit instructions stored in program memory are copied to the instruction register for decoding; each instruction contains both the operation code and operand. The instruction decoder logic converts the op-code bits into settings for all the internal control lines. The operand provides a literal, file register address or program address, which will be used by the instruction.

If, for example, the instruction is MOVLW (Move a Literal into W), the control lines will be set up to feed the literal operand to W via literal data bus to the multiplexer and ALU. If the instruction is MOVWF, the control lines will be set up to copy the contents of W to the specified file register via the internal data bus. The operand will be the address of the file register (00 to 4F) required. If we look at the 'move' instruction codes quoted in the instruction set, we can see the difference in the code structure for the three move instructions:

MOVLW k = 11 00xx kkkk kkkk

MOVWF f = 00 0000 1fff ffff

MOVF f,d = 00 1000 dfff ffff

In the MOVLW instruction, the operation code is the high 4 bits (1100), 'x' are 'don't care' bits, and 'k' represents the literal bits, the low byte of the instruction. In the MOVWF instruction, the operation code is 0000001 (7 bits) and 'f' bits specify the file register address. Only 7 bits are used for the register address, allowing a maximum of 2⁷ = 128 registers to be addressed. In the MOVF instruction the operation code is 001000, and the file register address is needed as before to identify the data source register. Bit 7 (d) controls the data destination. This bit must be 0 to direct the data into W, the usual operation. For example, to move an 8-bit data word from file register 0C to W requires the syntax MOVF 0C,W.

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How Microcomputers Work

Louis E. FrenzelJr., in Electronics Explained (Second Edition), 2018

Control Unit

CPUs also have several other registers, including the instruction register (IR); the program counter (PC), also called the instruction counter; and the memory address register (MAR), also called the address buffer.

The IR is used to store the instruction word. When the CPU fetches an instruction from memory, it is temporarily stored in the IR. The instruction is a binary word or code that defines a specific operation to be performed. The instruction word is also called the op code or operation code. The CPU decodes the instruction, and then executes it.

The PC is really a counter and a register. It stores a binary word that is used as the address for accessing the instructions in a program. If a program begins with an instruction stored in memory location 43, the PC is first loaded with the address 43. The address in the PC is applied to the memory, causing the instruction in location 43 to be fetched and executed. After the instruction is executed, the PC is incremented (add 1) to the next address in sequence, or 44. The instructions in a program are stored in sequential memory locations.

The MAR or address buffer also stores the address that references memory. This register directly drives the address bus and the memory address decoder in RAM or ROM. The MAR gets input from the PC when an instruction is to be accessed (see Fig. 6.7). The MAR can also be loaded with an address that is used to access data words stored in memory. To retrieve a data word used in an arithmetic operation, the MAR is loaded with the binary word that points to the location of that word in RAM. This address is often a part of the instruction.

It is important to note that the PC and the MAR (address buffer) have a fixed length of so many bits. And that limits the amount of memory that can be accessed. For example, with a 16-bit address register, the address bus has 16 bits to address RAM and ROM. With 16 bits, a maximum of 2¹⁶ = 65,536 words can be addressed.

There are usually two other registers, the flag and stack pointer registers. The flag or F register is an 8-bit register whose individual flip-flops are set and reset by the ALU as the various arithmetic and logic operations are carried out. Each flip-flop is called a flag. As an example, there are zero (Z) and carry (C) flags. If the accumulator content is zero after an operation is performed, the Z flag is set indicating this condition. If an arithmetic operation (addition) results in a carry from the most significant bit (MSB) of the accumulator, the C flag is set indicating this condition. These flags can be monitored or tested by the control circuitry to change the sequence of processing.

The stack register is a 16-bit or larger register used to address a selected area of RAM known as the stack. This memory is used to store register contents and status information when subroutines and interrupts are used.

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Microcontroller Operation

Martin Bates , in PIC Microcontrollers (Third Edition), 2011

2.1.3 Instruction Register and Decoder

To execute an instruction, the processor copies the instruction code from the program memory into the instruction register (IR). It can then be decoded (interpreted) by the instruction decoder, which is a combinational logic block which sets up the processor control lines as required. These control lines are not shown explicitly in the block diagram, as they go to all parts of the chip, and would make it too complicated. In the PIC, the instruction code includes the operand (working data), which may be a literal value or register address. For example, if a literal (a number) given in the instruction is to be loaded into the working register (W), it is placed on an internal data bus and the W register latch enable lines are activated by the timing and control logic. The internal data bus can be seen in the manufacturer's block diagram ( Figure 1-1 in the PIC 16F84A data sheet).

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Computer design

G.R. Wilson , in Embedded Systems and Computer Architecture, 2002

5.4.3 Operation of Simple Machine

The machine is designed to operate by repeating the following two phases for every instruction in the program.

Phase 1 – Instruction fetch

The Control Unit generates the control signals that copy an instruction byte from the memory into the Instruction Register, IR. The address of this instruction is in the Program Counter, PC.

Phase 2 – Instruction execute

The 8 bits in the IR are connected to the Control Unit. These 8 bits determine the sequence of control signals that the Control Unit generates. The sequence of control signals generated by the Control Unit causes the execution of the instruction. The sequence finishes by starting Phase 1, so fetching the next instruction into the IR.

The Control Unit is a complex sequential circuit having inputs from the IR that determine the sequence of control signals that the Control Unit generates. The system clock signal determines the timing of all these control signals. There are a large number of control signals. Thus there will be a control signal that is connected to the enable input of a three-state buffer that connects a register to a bus. There will be other signals that are connected to the load input of every register so causing that register to be loaded from the bus. Yet other signals will go to the ALU_mode control signals of the ALU causing the ALU to be set to perform a particular arithmetic or logical operation. Another control signal is connected to the WriteEnable input of the memory so determining whether the memory will read or write.

These signals will be asserted one after the other, so producing the sequence of control signals that cause the instruction to be fetched into the IR and then to be executed. For example, if the pattern of bits in the IR represents an instruction to copy data from one register to another, the sequence of control signals will be similar to that described in section 5.3.

The Control Unit is the most complex of the major components of the computing machine. We shall consider its design in Chapter 13.

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Microprocessors

DJ Holding BSc(Eng), PhD, CEng, FIEE, MBCS, MIEEE , in Electrical Engineer's Reference Book (Sixteenth Edition), 2003

15.4.3.2 Instruction register

This register holds the current instruction so that it can be decoded and input to the control and timing unit. Specifically, the instruction register holds the opcode which defines the type of instruction. Depending on the type of instruction, it may also hold immediate operand data or the addresses of operands and the address of the resultand. Since operand data and addresses comprise many bits, they are commonly held in temporary registers which can be considered as extensions to the instruction register. The contents of the instruction register can not be overwritten by the ALU, nor can they be accessed by a programmer.

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The control unit

G.R. Wilson , in Embedded Systems and Computer Architecture, 2002

13.7.2 Selecting a sequence

The CROM sequence required to execute an instruction such as ld a,(hl ) is determined by the operation code stored in the Instruction Register, IR, of the computer. An obvious possibility is to use the contents of the IR as the CROM address at which the control signal sequence for that instruction begins. That is, we load the CAR from the IR. We immediately recognize a problem: two operation codes may differ numerically by one. Thus 0×57 and 0×58 may both be legitimate operation codes in the computer so the sequence to execute the instruction with operation code 0×57 must occupy only one location in the CROM. There is a simple solution: CROM location 0×57 will contain a Next Address that refers to an unused location in the CROM where a sequence of any length may be placed. We will adopt this solution. The question now is how is the instruction fetch phase of the computer operation to be implemented?

For example, we will design our CROM contents so that the instruction fetch sequence occupies CROM locations 0×1E and 0×1F. This sequence of Control Signals is assumed to copy the next operation code from the RAM into the Instruction Register and into the CROM Address Register. At the end of each execution sequence, the Next Address field will be 0×1E so that the sequence to fetch the operation code of the next instruction will begin. This scheme is outlined in Figure 13.9. For simplicity, it is assumed that there are only four operation codes, 0×00 to 0×03.

Run program CROMA.exe and click on Enable Fetch in the menu. This loads the CROM with the data in Figure 13.9 and loads the CROM Address Register with 0×1E. Slowly click the Step button to see the Fetch sequence copy an operation code from RAM and then enter the appropriate Execute sequence. If you wish, you can change the program code in the RAM by clicking on RAM in the menu. (Remember that only 00 to 03 are valid op codes.)

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Case Study: System Design Using the Gumnut Core

Peter J. Ashenden , in The Designer's Guide to VHDL (Third Edition), 2008

Performing a Jump Instruction

The procedure for performing jump instructions is shown below. In the case of a jmp instruction, the procedure simply copies the target address from the instruction register to the program counter. In the case of a jsb instruction, before updating the program counter, the procedure first copies the current program counter value to the stack location indexed by SP, then increments SP. The increment is done using modulo arithmetic. If subroutine calls are nested too deeply, the earlier return address is overwritten with later addresses. The Gumnut does not check for this, as it has no mechanism for dealing with the error. Rather, it relies on the programmer or a compiler to avoid the error condition.

procedure perform_jump is

begin

case IR_jump_fn is

when jump_fn_jmp =>

PC := IR_addr;

when jump_fn_jsb =>

stack(SP) := PC;

SP := (SP + 1) mod stack_depth;

PC := IR_addr;

when others =>

report "Program logic error in interpreter"

severity failure;

end case;

end procedure perform_jump;

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The Processor

HARVEY M. DEITEL , BARBARA DEITEL , in An Introduction to Information Processing, 1986

The Instruction Execution Cycle

Now let's consider the execution of a typical machine language instruction in more detail. The computer must always know which location in main storage contains the next instruction to be executed. For this purpose, there is a special register in the CPU called the instruction counter. After each instruction is performed, the CPU automatically updates the instruction counter with the address of the next instruction to be performed.

Suppose the instruction counter contains address 5000. The computer fetches the instruction from location 5000 and places it into another special register in the CPU called the instruction register . The electronic components of the computer are designed in such a way that the computer can determine what type of instruction is in the instruction register—an addition, a subtraction, an input operation, an output operation, an edit operation, a comparison, and so on. If a computer's instruction register contains a multiplication instruction such as

the instruction is to multiply the 4-byte number starting in location 6000 by the 3-byte number starting in location 7500 and deposit the result in the 4-byte field at 6000.

The CPU proceeds as follows. First it fetches the 4-byte number from locations 6000 to 6003 and loads it into a register in the ALU. Then it fetches the 3-byte number from locations 7500 to 7502 and loads it into another register in the ALU. The product of the two values in the ALU registers is then calculated and deposited into a third ALU register. The CPU then stores this result back into the 4-byte field beginning at location 6000. (If the multiplication results in a number larger than four bytes, an overflow error has been made. Most computers will terminate a program when such a serious error occurs. For this reason, overflow is called a fatal error).

In short, most computers use the following scheme:

1.: Fetch the next instruction from the address indicated in the instruction counter and place it in the instruction register.
2.: Fetch the data to be operated upon and place it in registers in the ALU.
3.: Perform the indicated operation.
4.: Store the result of the operation back into main storage.

Why all this shuttling of instructions and data? Why not simply perform the calculations directly in the computer's main storage?

It is useful here to compare the operation of a computer system to that of a hospital with hundreds of rooms for patients and only a single operating room. A patient who requires surgery is moved from his or her own room and taken to the operating room. After the operation the patient is returned to his or her room, and the next patient is taken to the operating room. It would be too costly to provide each of the several hundred patient rooms with the expensive equipment required in an operating room.

Similarly, operations on data can only be performed in the CPU, so data is brought from main storage to the CPU. It remains there while it is being operated on and is returned to main storage when the operation is completed. The electronics required to perform operations is kept busy in much the same way that the hospital's operating room is kept busy.

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Device Drivers

Tammy Noergaard , in Embedded Systems Architecture (Second Edition), 2013

Interrupt Handling Enable on MPC860

// specific enabling of particular interrupts done in initialization section of this example -

// so the interrupt enable of all interrupts takes effect with the mtspr instruction.

mtspr 80,0; // enable interrupts via mtspr (move to special purpose

// register) instruction

// in review, to enable specific interrupt means modifying the SIMASK, so enabling the

// external interrupt at level 7 (IRQ7) for example is done by setting bit 14

SIMASK.IRM7="SIMASK.IRM7" OR "1"; // enable external interrupt input level 7

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